Configuration

Cortex-M Series:

Vendor:

Number of IRQs:

Add Exception/IRQ Handler

Handler Name:

IRQ Number:

Priority (0-15):

Description:

Vector Table

System Exceptions

Exception #	Offset	Name	Description	Priority

External Interrupts (IRQs)

IRQ #	Vector #	Offset	Handler	Description	Priority	NVIC Addr	Actions

NVIC Register Mapping

Enable Registers (ISER)

Priority Registers (IPR)

Export Code

About ARM Cortex-M IVT Generator

A powerful tool for ARM Cortex-M developers to build and export interrupt vector tables (IVT) with exception handlers, priorities, and NVIC register mappings. Perfect for prototyping startup code without needing to compile.

Features:

Support for Cortex-M0, M0+, M3, M4, M7, M33, M55
Configure system exceptions and external interrupts
Set interrupt priorities (0-15)
Visual vector table with offsets and addresses
NVIC register mapping (ISER, ICER, IPR)
Export to Assembly (.s), C (.c), Linker Script (.ld)
Generate CMSIS-compatible initialization code
JSON export for further processing
Vendor-specific templates (STM32, Nordic, Microchip, NXP)
Calculate NVIC register addresses automatically

How to Use:

Select Configuration: Choose Cortex-M series, vendor, and number of IRQs
Add Handlers: Define ISR handlers with names, IRQ numbers, and priorities
Review Table: View the complete vector table with system exceptions and IRQs
Check NVIC Mapping: See which NVIC registers control each interrupt
Export Code: Generate assembly, C, or linker script for your project

ARM Cortex-M Vector Table Structure:

Offset Exception # Handler
0x0000 - Initial SP value
0x0004 1 Reset_Handler
0x0008 2 NMI_Handler
0x000C 3 HardFault_Handler
0x0010 4 MemManage_Handler (M3+)
0x0014 5 BusFault_Handler (M3+)
0x0018 6 UsageFault_Handler (M3+)
...
0x0040 16 IRQ0_Handler (first external interrupt)

NVIC Registers:

ISER (Interrupt Set-Enable): Enable interrupts (0xE000E100 + n*4)
ICER (Interrupt Clear-Enable): Disable interrupts (0xE000E180 + n*4)
IPR (Interrupt Priority): Set priority (0xE000E400 + n)
ISPR/ICPR: Set/Clear pending bits
IABR: Active bit registers (read-only)

Priority Grouping:

Cortex-M processors support configurable priority grouping via SCB->AIRCR[10:8] (PRIGROUP). This determines how the priority byte is split into preemption priority and sub-priority. Most applications use group priority 0 (all bits for preemption).

Common Use Cases:

Startup Code: Generate vector table for new Cortex-M projects
Learning: Understand ARM exception handling architecture
Prototyping: Test ISR configurations before compiling
Documentation: Create visual interrupt documentation
Porting: Migrate vector tables between vendors/devices
Debugging: Verify NVIC register addresses and priorities

Tips:

System exceptions (-3 to 15) have fixed vector positions
External interrupts (IRQ0-IRQn) start at vector 16 (offset 0x0040)
Lower priority numbers = higher priority (0 is highest)
Each ISER/ICER register controls 32 interrupts (bit per IRQ)
IPR registers pack 4 priorities per 32-bit word (1 byte each)
Use default handler for unused interrupts (infinite loop or reset)
The Reset_Handler should initialize .data/.bss before calling main()

William Shane Burrell

ARM Cortex-M Interrupt Vector Table Generator - NVIC Configuration Tool